The present invention relates to a video data shuffling method and apparatus, and more particularly, to a video data shuffling method and apparatus for shuffling video data using a single memory.
In general, a digital video cassette recorder (VCR) shuffles video data in a predetermined range, for example, one frame according to a predetermined rule. Shuffling system of video data using an interlace addressing method and a shuffle addressing method according to an existing digital VCR standard will be described with reference to FIGS. 1A through 2G.
Video data of one frame is stored in a memory according to an interlace addressing method. To store video data of one frame in a memory, the interlace addressing method writes the video data of one frame on the memory in sequence from left to right for each line, in sequence from a second uppermost line to following even numbered lines for an odd field, and in sequence from a first uppermost line to following odd-numbered lines for an even field. Video data of one frame stored in the memory according to the interlace addressing method are divided into 50 super blocks as shown in FIG. 1A in the case of 525/60 system such as NTSC, and are divided into 60 super blocks as shown in FIG. 1B in the case of 625/50 system such as PAL. Each super block is composed of 27 macro blocks, and each macro block is composed of 6 discrete cosine transformation (DCT) blocks.
FIGS. 2A and 2G are views for explaining an shuffle addressing method according to an existing digital VCR standard to read video data stored in the memory. Referring to FIG. 2A, the shuffle addressing method performs a reading operation with respect to one DCT block having the size of 8.times.8 pixels, in sequence, from left to right in each line and from the upper line to the lower line for lines. Each macro block contained in a super block is classified into two types shown in FIGS. 2B and 2C. A-type macro block is composed of 6 DCT blocks as shown in FIG. 2B and the 6 DCT blocks are read in an ascending order of individually assigned numbers. That is, the DCT blocks contained in an A-type macro block are read in sequence from the left-most DCT block to the right most DCT block. B-type macro block is composed of 6 DCT blocks which are arranged in the form of a 3.times.2 array as shown in FIG. 2C. The DCT blocks belonging to the B-type macroblock also are read in an ascending order of individually assigned numbers. That is, two DCT blocks of each row are read in sequence from left to right and the rows of DCT blocks are read in sequence from the upper row of DCT blocks to the lower row of DCT blocks.
Referring to FIG. 2D showing three types of super block for the 525/60 system, macro blocks constituting each super block are read out from the memory in sequence from the lowest number to the highest number. In FIG. 2D, two types of super block located in relatively left-hand side are composed of the above-described A-type macro blocks, and different type of super block located in the right-hand side is composed of the A-type macro blocks and the B-type macro blocks which are indicated as numbers 24, 25 and 26. Referring to FIG. 2E showing a super block for the 625/50 system, the super block is composed of the above-described B type macro blocks which are read out in sequence from the lowest number to the highest number.
FIG. 2F shows super block arrangement for the 525/60 system, and FIG. 2G shows super block arrangement for the 625/50 system. As can be seen via comparison of FIGS. 2F and 2G, the super block arrangement for the 525/60 system is substantially the same as that for the 625/50 system. Therefore, video data of each frame in the 525/60 and that of the 625/50 systems are read out from a memory in the substantially same read sequence. When reading out super blocks of each system from the memory, assuming that numbers 0, 1, 2, 3, 4 and 5 are respectively assigned to each of super block columns in sequence from the left-most to the right-most, the super block columns can be read in sequence of 2, 1, 3, 0 and 4. Among the super blocks belonging to every super block column, the super block indicated as number "0" is read out firstly. For example, in one frame for the 525/60 system, a super block indicated as number "0" within a third super block column from the left-most of FIG. 2F is read out for the first time, and a super block indicated as number "0" in the second super block column from the left most of FIG. 2F is read out for the second time.
When video data is shuffled using the above-described shuffling system and a single memory, video data of one frame can be read via shuffle addressing only if the video data of the one frame is completely stored in the single memory via interlace addressing. Therefore, a new addressing method is required to continuously shuffle video data of a sequential frame using a single memory.